View 840022AKI-02LF_8848944.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet ics840022aki-02 may 27, 2017 1 ?2017 integrated device technology, inc. femtoclock ? crystal-to-lvcmos/lvttl clock generator ics840022i-02 general description the ics840022i-02 is a gigabit ethernet clock generator. the ics840022i-02 uses a 25mhz crystal to synthesize 125mhz or 62.5mhz. the ics840022i-02 has excellent phase jitter performance, over the 12khz ? 20mhz integration range. the ics840022i-02 is packaged in a small 16-pin vfqfn, making it ideal for use in systems with limited board space. features ? one lvcmos/lvttl outputs, 20 ? output impedance ? crystal oscillator interface designed for 25mhz, 18pf parallel resonant crystal ? output frequencies: 125mhz or 62.5mhz ? rms phase jitter at 125mhz using a 25mhz crystal (12khz - 20mhz): 0.57ps (typical) ? supply modes: core/output 3.3v/3.3v 3.3v/2.5v 2.5v/2.5v ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package function table inputs output frequency range (with a 25mhz crystal) freq_sel 0 125mhz 1 62.5mhz osc phase detector vco m = 25 (fixed) 0 1 10 5 q xtal_in xtal_out f req_sel pulldown pwr_dn pullup 25mhz 5 6 7 8 16 15 14 13 1 2 3 4 12 11 10 9 pwr_dn x tal_out xtal_in gnd q nc v dd o v dd gnd nc f req_sel gnd nc nc gn d v dd ics840022i-02 16 lead vfqfn top view pin assignment block diagram
ics840022aki-02 may 27, 2017 2 ?2017 integrated device technology, inc. ics840022i-02 data sheet femtoclock ? crystal-to-lvcmos/lvttl clock generator table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function table table 3. pwr_dn function table number name type description 1 pwr_dn input pullup output state control pin. see table 3. lvcmos/lvttl interface levels. 2, 3 xtal_out, xtal_in input crystal oscillator interface. xtal_in is the input. xtal_out is the output. 4, 5, 8, 13 gnd power power supply ground. 6, 11, 14, 15 nc unused no connect. 7 freq_sel input pulldown frequency select pin. lvcmos/lvttl interface levels. 9, 16 v dd power power supply pins. 10 v ddo power output supply pin. 12 q output single-ended clock output. 20 ? typical output impedance. lvcmos/lvttl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4pf c pd power dissipation capacitance v dd, v dd = 3.465v or 2.625v 10 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance 20 ? pwr_dn input description 0 output in high-impedance 1 output in normal operation
ics840022aki-02 may 27, 2017 3 ?2017 integrated device technology, inc. ics840022i-02 data sheet femtoclock ? crystal-to-lvcmos/lvttl clock generator absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c table 4b. power supply dc characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85c table 4c. power supply dc characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ? ja 74.9 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditions minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current pwr_dn = 1 77 ma pwr_dn = 0 <1 ma i ddo output supply current 12 ma symbol parameter test conditions minimum typical maximum units v dd power supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current pwr_dn = 1 68 ma pwr_dn = 0 <1 ma i ddo output supply current 10 ma symbol parameter test conditions minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current pwr_dn = 1 77 ma pwr_dn = 0 <1 ma i ddo output supply current 10 ma
ics840022aki-02 may 27, 2017 4 ?2017 integrated device technology, inc. ics840022i-02 data sheet femtoclock ? crystal-to-lvcmos/lvttl clock generator table 4d. lvcmos/lvttl dc characteristics, t a = -40c to 85c note 1: outputs terminated with 50 ? to v ddo /2. see parameter measurement information, output load test circuit diagrams. table 5. crystal characteristics symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd = 3.465v 2 v dd + 0.3 v v dd = 2.625v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.465v -0.3 0.8 v v dd = 2.625v -0.3 0.7 v i ih input high current freq_sel v dd = v in = 3.465v or 2.625v 150 a pwr_dn v dd = v in = 3.465v or 2.625v 5 a i il input low current freq_sel v dd = 3.465v or 2.625v, v in = 0v -5 a pwr_dn v dd = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage; note 1 v ddo = 3.465v 2.6 v v ddo = 2.625v 1.8 v v ol output low voltage; note 1 v ddo = 3.465v or 2.625v 0.5 v parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf
ics840022aki-02 may 27, 2017 5 ?2017 integrated device technology, inc. ics840022i-02 data sheet femtoclock ? crystal-to-lvcmos/lvttl clock generator ac electrical characteristics table 6a. ac characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85 note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note 1: refer to phase noise plot. table 6b. ac characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85 note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note 1: refer to phase noise plot. table 6c. ac characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = -40c to 85 note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. symbol parameter test conditions minimum typical maximum units f out output frequency freq_sel = 0 125 mhz freq_sel = 1 62.5 mhz t jit(?) rms phase jitter, random; note 1 125mhz, integration range: 12khz ? 20mhz 0.57 ps 62.5mhz, integration range: 12khz ? 10mhz 0.58 ps t r / t f output rise/fall time 20% to 80% 200 700 ps odc output duty cycle 47 53 % symbol parameter test conditions minimum typical maximum units f out output frequency freq_sel = 0 125 mhz freq_sel = 1 62.5 mhz t jit(?) rms phase jitter, random; note 1 125mhz, integration range: 12khz ? 20mhz 0.62 ps 62.5mhz, integration range: 12khz ? 10mhz 0.58 ps t r / t f output rise/fall time 20% to 80% 200 700 ps odc output duty cycle 47 53 % symbol parameter test conditions minimum typical maximum units f out output frequency freq_sel = 0 125 mhz freq_sel = 1 62.5 mhz t jit(?) rms phase jitter, random 125mhz, integration range: 12khz ? 20mhz 0.62 ps 62.5mhz, integration range: 12khz ? 10mhz 0.58 ps t r / t f output rise/fall time 20% to 80% 200 750 ps odc output duty cycle 47 53 %
ics840022aki-02 may 27, 2017 6 ?2017 integrated device technology, inc. ics840022i-02 data sheet femtoclock ? crystal-to-lvcmos/lvttl clock generator typical phase noise at 62.5mhz (3.3v) typical phase noise at 125mhz (3.3v) gb ethernet filter phase noise result by adding a gb ethernet filter to raw data raw phase noise data 62.5mhz rms phase jitter (random) 12khz to 10mhz = 0.58ps (typical) offset frequency (hz) noise power dbc hz gb ethernet filter phase noise result by adding a gb ethernet filter to raw data raw phase noise data 125mhz rms phase jitter (random) 12khz to 20mhz = 0.57ps (typical) offset frequency (hz) noise power dbc hz
ics840022aki-02 may 27, 2017 7 ?2017 integrated device technology, inc. ics840022i-02 data sheet femtoclock ? crystal-to-lvcmos/lvttl clock generator parameter measurement information 3.3v lvcmos output load ac test circuit 2.5v lvcmos output load ac test circuit output rise/fall time 3.3v/2.5v lvcmos output load ac test circuit rms phase jitter output duty cycle/pulse width/period scope q lvcmos gnd v dd, , v ddo 1.65v5% -1.65v5% scope q lvcmos gnd v dd, v ddo 1.25v5% -1.25v5% 20% 80% 80% 20% t r t f q scope q lvcmos gnd 2.05v5% -1.25v5% v dd v ddo 1.25v5% phase noise ma sk offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power t period t pw t period odc = v ddo 2 x 100% t pw q
ics840022aki-02 may 27, 2017 8 ?2017 integrated device technology, inc. ics840022i-02 data sheet femtoclock ? crystal-to-lvcmos/lvttl clock generator applications information crystal input interface the ics840022i-02 has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 1 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. figure 2. crystal input interface overdriving the xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 2a. the xtal_out pin can be left floating. the maximum amplitude of the input signal should not exceed 2v and the input edge rate can be as slow as 10ns. this configuration requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . by overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. figure 2a. general diagram for lvcmos driver to xtal input interface figure 2b. general diagram for lvpecl driver to xtal input interface xtal_in xtal_out x1 1 8pf parallel crystal c1 27pf c2 27pf
ics840022aki-02 may 27, 2017 9 ?2017 integrated device technology, inc. ics840022i-02 data sheet femtoclock ? crystal-to-lvcmos/lvttl clock generator recommendations for unused input pins inputs: lvcmos control pins the control pins have an internal pullup and pulldown; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 3. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 3. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics840022aki-02 may 27, 2017 10 ?2017 integrated device technology, inc. ics840022i-02 data sheet femtoclock ? crystal-to-lvcmos/lvttl clock generator reliability information table 7. ? ja vs. air flow table for a 16 lead vfqfn transistor count the transistor count for ics840022i-02 is: 1760 ? ja at 0 air flow meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 74.9 ? c/w 65.5 ? c/w 58.8 ? c/w
ics840022aki-02 may 27, 2017 11 ?2017 integrated device technology, inc. ics840022i-02 data sheet femtoclock ? crystal-to-lvcmos/lvttl clock generator package outline drawings (sheet 1)
ics840022aki-02 may 27, 2017 12 ?2017 integrated device technology, inc. ics840022i-02 data sheet femtoclock ? crystal-to-lvcmos/lvttl clock generator package outline drawings (sheet 2)
ics840022aki-02 may 27, 2017 13 ?2017 integrated device technology, inc. ics840022i-02 data sheet femtoclock ? crystal-to-lvcmos/lvttl clock generator ordering information table 9. ordering information note: parts that are ordered with an ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 840022AKI-02LF 0i2l ?lead-free? 16 lead vfqfn tube -40 ? c to 85 ? c 840022AKI-02LFt 0i2l ?lead-free? 16 lead vfqfn 2500 tape & reel -40 ? c to 85 ? c
ics840022i-02 data sheet femtoclock ? crystal-to-lvcmos/lvttl clock generator 14 ?2017 integrated device technology, inc. disclaimer integrated device technology, inc. (idt) and its affiliated companies (herein referred to as ?idt?) reserve the righ t to modify the products and/or specifications described herein at any time, without notice, at idt?s sole discretion. performance specifications and operating parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual p roperty rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be rea- sonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology, inc.. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com revision history sheet rev table page description of change date a 1 8 corrected block diagram. updated vfqfn epad thermal release path section. 11/7/07 b t4c t6c 1 3 5 6 8 11 features section - added 3.3v/2.5v operating supply. added 3.3v/2.5v power supply dc characteristics table. added 3.3v/2.5v power supply ac characteristics table. added 3.3v/2.5v output load ac test circuit diagram. updated overdriving the crystal interface. updated package drawing. converted datasheet format. 7/28/10 b t9 12 ordering information table - corrected marking from ?012l? to ?0i2l?. 9/27/10 c - 11/12 updated the package outline drawings. 5/27/2017

▲Up To Search▲

Price & Availability of 840022AKI-02LF

	To Download 840022AKI-02LF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .